1. Field of the Invention
The present invention relates to a solid-state imaging device which can switch reading modes between an all pixel reading mode and a column thinning-out reading mode.
Priority is claimed on Japanese Patent Application No. 2008-333577, filed Dec. 26, 2008, the content of which is incorporated herein by reference.
2. Description of Related Art
As a solid-state imaging device used as an imaging device in an imaging device which converts light into electric signals and outputs image signals such as a digital still camera, a variety of research and development has been made regarding a MOS (Metal-Oxide Semiconductor) type solid-state imaging device (for example, see Japanese Unexamined Patent Application, First Publication No. 2006-93816 for reference).
For example, FIG. 8 shows a configuration of the MOS type solid-state imaging device according to the related art as an example, which can be operated in the all pixel reading mode or in the column thinning-out reading mode by switching therebetween.
The MOS type solid-state imaging device is constituted by pixel units 11 to 44 which are arranged in a matrix shape, a vertical scanning unit 2 which supplies reading pulses to the pixel units 11 to 44, vertical signal lines 3_1 to 3_4 which transmit signals from the pixel units 11 to 44, and a pixel bias current source IPIX which supplies a constant current to the vertical signal lines 3_1 to 3_4. The MOS type solid-state imaging device is constituted by column circuits 4_1 to 4_4 which process the signals of the vertical signal lines 3_1 to 3_4, sample-and-hold transistors M7_1 and M7_2 which are connected to each column circuit to hold signals from the column circuits, sample-and-hold capacitances Cs_1 and Cs_2, column selection transistors M8_1 and M8_2 which selectively output signals to horizontal signal lines 6_1 and 6_2 from the sample-and-hold capacitances Cs_1 and Cs_2 of each column, and horizontal scanning units 5_1 and 5_2 which supply pulses to the column selection transistors M8_1 and M8_2. The MOS type solid-state imaging device is constituted by horizontal signal line reset transistors M9_1 and M9_2 which reset the horizontal signal lines 6_1 and 6_2, output amplifiers 7_1 and 7_2 which amplify and output the signals of the horizontal signal lines 6_1 and 6_2, and a mode setting unit 8 which switches reading modes.
Each of the pixel units 11 to 44 is constituted by a photodiode PD which converts incident light into an electric signal, a transmission transistor M1 which transmits the electric signal stored in the photodiode PD, an amplifying transistor M3 which amplifies the transmitted electric signal, a reset transistor M2 which resets a potential of a gate of the amplifying transistor M3, and a row selection transistor M4 which selectively outputs an amplified signal based on the electric signal.
In the gates of the transmission transistor M1, the reset transistor M2, and the row selection transistor M4, transmission pulses φTX1 to φTX4, reset pulses φRST1 to φRST4, and row selection pulses φROW1 to φROW4 are input from the vertical scanning unit 2. In addition, a pixel power source VDD is connected to the drains of the reset transistor M2 and the amplifying transistor M3.
Each of the row circuits 4_1 to 4_4 is constituted by a clamp capacitance Cc and a clamp transistor M6 in order to clamp the output signal of each of the pixel units 11 to 44 on a clamp potential VC, so that the noise components included in the pixel signals are reduced. A clamp pulse φCL is input to the gate of the clamp transistor M6.
In addition, a sample-and-hold pulse φSH1 is input to the gates of the sample-and-hold transistors M7_1. A sample-and-hold pulse φSH2 is input to the gates of the sample-and-hold transistors M7_2.
The column selection pulses φH1_1 to φH4_1 are input to the gates of the column selection transistors M8_1 of the respective columns. The column selection pulses φH1_2 to φH4_2 are input to the gates of the column selection transistors M8_2 of the respective columns. The horizontal signal line reset pulses φRS1 and φRS2 are input to the gates of the horizontal signal line reset transistors M9_1 and M9_2. A horizontal signal line reset voltage source VR is connected to the drains of the horizontal signal line reset transistors M9_1 and M9_2.
Using the timing chart shown in FIG. 9, the outline of the operations of the MOS type solid-state imaging device according to the related art shown in FIG. 8 will be described. Further, in the following description, a high level of a voltage is expressed by “H” level, and a low level thereof is expressed by “L” level.
FIG. 9 is a timing chart of the all pixel reading mode in which the signals are read from all of the pixels.
First, a reading operation becomes possible to be performed on the pixel units 11 to 14 in a first row by the vertical scanning unit 2. When the row selection pulse φROW1 ascends to the H level, the row selection transistors M4 come to be in the ON state. The output signals of the amplifying transistors M3 are output to the vertical signal lines 3_1 to 3_4, respectively. In addition, when the reset pulse φRST1 ascends to the H level, the reset transistors M2 come to be in the ON state. The gates of the amplifying transistors M3 are reset to a reset potential. The output signals corresponding to the reset potential of the pixel units 11 to 14 are output to the vertical signal lines 3_1 to 3_4, respectively. At this time, the clamp pulse φCL ascends to the H level, so that the clamp transistors M6 come to be the ON state and the clamp capacitances Cc are clamped on a clamp potential VC. In addition, when the sample-and-hold pulse φSH1 ascends to the H level, the sample-and-hold transistors M7_1 come to be in the ON state, so that the sample-and-hold capacitances Cs_1 come to be in a sampling state (see time t2).
Next, after the reset pulse φRST1 descends to the L level (see time t3), the clamp pulse φCL descends to the L level and the clamping is ended (see time t4). In addition, the transmission pulse φTX1 ascends to the H level, so that the transmission transistors M1 come to be in the ON state. The electric signals according to the light signals generated by the photodiodes PD are transmitted to the amplifying transistors M3 (see time t5). The transmission pulse φTX1 descends to the L level. Therefore, the amplified signals of the electric signals according to the light signals of the pixel units are output to the vertical signal lines 3_1 to 3_4. The output signals of the column circuits 4_1 to 4_4 are changed by amounts ΔSig which is caused by the electric signals according to the light signals from the reset potential of the pixel units 11 to 14 due to the clamp capacitances Cc. The noise components included in the reset potential are reduced (see time t6).
When the sample-and-hold pulse φSH1 descends to the L level, the read signals from the column circuits 4_1 to 4_4 are held on the sample-and-hold capacitances Cs_1 of the respective columns (see time t7).
Next, when the horizontal signal line reset pulse φRS1 ascends to the H level, the horizontal signal line 6_1 is reset to the potential of the horizontal signal line reset voltage source VR. Thereafter, when the horizontal signal line reset pulse φRS1 descends to the L level and the column selection pulse φH1_1 ascends to the H level, the output signal of the column circuit 4_1 which is held on the sample-and-hold capacitance Cs_1 is read out to the horizontal signal line 6_1 (see time t10).
The reset operation in which the potential of the horizontal signal line 6_1 becomes the potential of the horizontal signal line reset voltage source VR, and the reading operation of the signals which are held on the sample-and-hold capacitances Cs_1 are repeated. The signals of the first row which are held on the sample-and-hold capacitances Cs_1 are sequentially read out to the horizontal signal line 6_1. The signals are output from the output channel OUT1 via the output amplifier 7_1.
Furthermore, when the signals of the first row are read out to the horizontal signal line 6_1, the pixel signals of the second row are read out similarly to the first row. Similarly to the first row, the pixel signals of the second row, in which the noise components are canceled via the column circuits, are held on the sample-and-hold capacitances Cs_2. (see time t11 to time t19).
When the reading operation of the pixel signals of the first row which are held on the sample-and-hold capacitances Cs_1 is ended (see time t18), a reading operation is continuously performed in which the pixel signals of the second row held on the capacitances Cs_2 are read out to the horizontal signal line 6_2 (see time t21). The reset operation in which the potential of the horizontal signal line 6_1 becomes the potential of the horizontal signal line reset voltage source VR, and the reading operation of the signals which are held on the sample-and-hold capacitances Cs_1 are repeated. Therefore, the reading operation of the signals is carried out on the pixel units (see time t21 to time t28).
As described above, the reading operation in which the pixel signals of the Nth row are read out to the horizontal signal line, the reading operation in which the pixel signals of the (N+1)th row are read out to the column circuits, and the noise canceling process in the column circuits are simultaneously carried out. Therefore, the reading operations can be rapidly carried out.